One prior art technique for controlling the etching depth into a film requires embedding etch stop layers at the required trench depth. The etching solution etches the film at a higher rate than the etch stop layer allowing finer control of the depth. While this works acceptably for multiple films deposited on a substrate, e.g. dual damascene process in CMOS technology, it is not practical for etching into a substrate or a very thick homogeneous film.
Another prior art technique, typically used in micro-electromechanical system (MEMS) applications, is to use a silicon-on-insulator (SOI) wafer. The etch stop layers are embedded into the insulator layer. This restricts the manufacturing process to layered silicon-insulator-silicon substrates. Adding etch stop layers into the insulator layer is costly and adds to their manufacturing process complexity.
With both techniques, the embedded etch stop layers can interfere with the morphology and the growth phase of the device film.